High-temperature ovens, called reactors, are used to create structures of very fine dimensions, such as integrated circuits on semiconductor wafers or other substrates. A circular substrate, typically a silicon wafer, is placed on a wafer support. Both the wafer and support are heated, typically by a plurality of radiant lamps placed around a quartz chamber. In a typical process, a reactant gas is passed over the heated wafer, causing the chemical vapor deposition (CVD) of a thin layer of the reactant material on the wafer. Through subsequent processes, these layers are made into integrated circuits, with a single layer producing from tens to thousands of integrated circuits, depending on the size of the wafer and the complexity of the circuits. Other processes include sputter depositions, photolithography, dry etching, plasma processes, and high temperature anneals. Many of these processes require high temperature steps and can be performed in similar quartz reaction chambers.
If the deposited layer has the same crystallographic structure as the underlying silicon wafer, it is called an epitaxial layer. This is also sometimes called a monocrystalline layer because it has only one crystal structure.
Various process parameters must be carefully controlled to ensure the high quality of the resulting layers. One such critical parameter is the temperature of the wafer during the processing. During CVD, for example, the deposition gas reacts at particular temperatures and deposits on the wafer. If the temperature varies greatly across the surface of the wafer, uneven deposition of the reactant gas occurs.
In certain batch processors (i.e., reactors which process more than one wafer at a time) wafers are placed on a relatively large-mass susceptor made of graphite or other heat-absorbing material to help the temperature of the wafers remain uniform. In this context, a “large-mass” susceptor is one which has a large thermal mass relative to the wafer. The thermal mass of a solid, or its lumped thermal capacitance, is given by the equation:CT=ρVcwhere:                ρ=the density of the solid,        V=the volume of the solid, and        c=the specific heat (heat capacity) of the solid.Thus, the thermal mass is directly related to its mass, which is equal to the density times volume and to its specific heat.        
One example of a large-mass susceptor is shown in U.S. Pat. No. 4,496,609 issued to McNeilly, which discloses a CVD process wherein the wafers are placed directly on a relatively large-mass slab-like susceptor and maintained in intimate contact to permit a transfer of heat therebetween. The graphite susceptor supposedly acts as a heat “flywheel” which transfers heat to the wafer to maintain its temperature uniform. The goal is to reduce transient temperature variations around the wafer that would occur without the “flywheel” effect of the susceptor.
Although large-mass susceptors theoretically aid in maintaining temperature uniformity across the wafers when the system is in a steady state, the large thermal mass of the susceptor makes the susceptor-wafer combination slow in responding to temperature transients (e.g., while heating up or cooling down the system). Accordingly, processing wafers with large-mass susceptors involves long thermal cycles, limiting the number of wafers which can be processed in a given length of time (i.e., limiting process throughput). High throughput remains a prime concern in single-wafer semiconductor processing.
In recent years, single-wafer processing of larger diameter wafers has grown for a variety of reasons including greater precision process control as compared to batch-processing. Typical wafers are made of silicon with one common size having a diameter of 200 mm and a thickness of 0.725 mm. Recently, larger silicon wafers having a diameter of 300 mm and a thickness of 0.775 mm have been introduced, as they even more efficiently exploit the benefits of larger single-wafer processing. Additionally, even larger wafers are contemplated for the future.
Although single-wafer processing by itself provides advantages over batch processing, control of the process parameters remains critical and is perhaps more so because of the increased cost of the larger wafers. One example of a single-wafer processor is shown in U.S. Pat. No. 4,821,674, which utilizes a circular rotatable susceptor having a diameter slightly larger than the wafer. This susceptor is preferably made of graphite and has a lower thermal mass than the aforementioned slab-type batch processing susceptor. Nevertheless, the thermal mass of a production version of the susceptor described in U.S. Pat. No. 4,821,674 is larger than the thermal mass of the single wafer, such that thermal cycle time for the system is limited.
U.S. Pat. No. 4,978,567 describes a wafer holding fixture of lower mass than conventional susceptors. The lower mass facilitates rapid heating and cooling of the wafer for Rapid Thermal Processing (RTP) systems. Throughput can also be increased in connection with other processes involving heating or cooling of a substrate to be processed.
Processing wafers with such a low-mass wafer holder, however, introduces new problems. For example, the low mass of the wafer holder, combined with a small gap between the wafer and holder, makes it difficult to lift a wafer off the holder without also lifting the wafer holder. A vacuum effect causes the wafer and holder to stick together. As gas starts to fill the small gap, the gap will increase and the gas will flow faster. Accordingly, the holder will drop shortly after pick-up. Obviously such an uncontrolled drop can cause damage to the wafer holder and surrounding equipment within the reaction chamber. Additionally, particulate matter created by such damage can contaminate processed wafers.
The very rapidity of thermal response for which the low mass wafer holder is designed can also cause damage to the wafer and to reactor parts. For example, when first introduced into a reaction chamber, the wafer may be cold (e.g., 200° C.), while the wafer holder remains hot (e.g., 900° C.) from processing a prior wafer. Bringing the cold wafer into contact with a hot wafer holder causes a rapid heat drain from the holder to the wafer. The low mass wafer holder rapidly drops in temperature, as compared to the rate at which a high mass susceptor would drop, until the wafer and wafer holder are in thermal equilibrium. The wafer, in the interim, undergoes a rapid heat influx. The rapid temperature fluctuation causes thermal shock to both the wafer and the holder. Both the wafer and-holder tend to bow under the strain of vertical and radial temperature gradients during the transition. The stress can often cause breakage of the wafer holder and, occasionally, even the wafer.
The lower mass wafer holder is also susceptible to thermal expansion during heating. Due to differences in equipment material, the wafer holder will tend to expand at a different rate, as compared to surrounding equipment. In particular, a structure for supporting and rotating the wafer holder during processing is often constructed of quartz, such that radiant heat from below will largely pass through this structure. A typical graphite or silicon carbide (SiC) wafer holder expands significantly more rapidly than the quartz structure.
Relative movement between the supporting quartz and the wafer holder due to differences in thermal expansion can cause decentering of the wafer holder and the wafer upon it. Decentering, in turn, can tilt the wafer holder or otherwise upset a carefully balanced relationship between reactor elements and the wafer, configured for achieving temperature uniformity. Furthermore, eccentricity will exacerbate the decentration, such that the wafer holder can come in contact with a slip ring or other adjacent structure, bumping or rubbing against these structures during rotation and potentially introducing particulate matter into the reactor. Decentering can thus cause non-uniformity in the quality and thickness of deposited layers, for instance.
Consequently, there is a need for an improved low mass wafer support structure to increase throughput of semiconductor processing devices while ensuring temperature uniformity across the wafer surface. Desirably, such a support structure should avoid the above-noted problems associated with wafer pick-up, thermal shock, and thermal expansion.